1. Field of the Invention
The present invention generally relates to a package structure and a package process, and more particularly, to a package structure and a package process having good process compatibility and good system-integrating capability.
2. Description of Related Art
It is always one of the major goals for long in the electronic manufacturing industry to minimize the volumes of IC component products. A compact product with a small volume means a lower production cost, shorter signal transmission paths and better product performances.
One of key factors affecting the volume of an IC component rests in the improvement of the packaging technology. Among the contemporary technologies, the way using a leadframe to serve as a chip carrier is a quite popular and wide applicable technique, wherein a common structure is quad flat package (QFP) structure.
Along with the promotion of process capability, the architecture of integrating multi chips into a system has played a major development role in the contemporary packaging technology. However, the increasing integrity extent of chip circuits demands more contact counts for import or output required by each chip. As a result, the conventional QFP structure where a leadframe is used as a chip carrier provides a limited lead quantity and layout thereof, and thereby can not meet the modern requirements. The limited lead quantity and layout thereof is also resulted in indirectly limiting the compatibility and the system-integrating capability of a QFP structure.